Dedicated and resourceful DSP Software/Firmware Engineer eager to contribute strong design and development expertise toward supporting a progressive employer in achieving goals and objectives.

 

 

• Consummate skills in digital signal processing (DSP) design, programming in C, and developing cutting-edge digital systems.
• Adept at partnering with vendors as well as individuals from other disciplines, functional areas, and departments to facilitate and ensure successful project outcomes.
• Well-developed ability to analyze and swiftly solve complex engineering problems.
• Proven success in identifying methods to improve product performance and interoperability.
• Able to interpret complex schematics, diagrams, blueprints, sketches, and specifications. 
• Equally effective working autonomously as well as within a collaborative environment.
• Excel throughout all development phases including algorithms, implementation, testing, and system integration.

 

 

Teranetics, Inc., San Jose, California (acquired by PLX Technology), 2006 to Present

Principal DSP Firmware Engineer

• Resourcefully developed company s first standard compliance 10GBase-T start-up firmware and produced first (130nm), second (65nm), and third (40nm) generation PHYs.
• Measurably improved SNR (signal-to-noise ratio) and BER (bit error rate) by optimizing gain settings and characterizing adaptive filters.
• Analyzed and implemented Infofield exchange (PBO/THP) and state transition algorithms.
• Allocated training time for each start-up state and achieved error-free 100m+ loop reach with two-second start-up training.
• Conducted interoperability test with other PHY vendors and swiftly resolved IOP issues.
• Applied sharp attention to detail toward monitoring timing drift from other vendors, tracking start-up time for each state, and resolving non-standard compliance issues. 
• Successfully integrated optional features such as power-saving mode and start-up EMI detection and cancellation.
• Spearhead software implementation for Energy Efficient Ethernet (EEE) and recommended hardware additions.
• Demonstrate exemplary technical and troubleshooting expertise in providing prompt and quality-driven customer support.

 

Centillium Communications Corporation, Fremont, California, 1999 to 2006

Staff DSP Firmware Engineer

• Collaboratively developed ADSL CO G.DMT (ITU G.992.1) from legacy G.lite (ITU G.992.2) on CopperFlite platform inclusive of memory layout, tone ordering, dual TC layer programming, and extending TX carrier from 96 to 224 bins.
• Engineered FEXT bit map and dual bit map modes, dying gasp and micro interruption on Annex-C CO on Electra-1 platform.
• Championed migration of ADSL DSP code from Electra-1 to Electra-2 platform to effectively decrease costs.

 

Continued

 

 

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Professional Experience continued

 

• Developed Annex-I (2x DS) and Annex-Q (4x DS) on Maximus platform, extending TX carriers to 869, programming HW Echo canceller, and expeditiously eliminating multi-channel issues.
• Merged strong communication skills with well-honed troubleshooting capabilities to provide post-production on-site customer support both locally and internationally (Japan, Korea, Europe).
• Directed, supervised and mentored Bangalore development team in ADSL 2+ (ITU G.992.3) project.

 

MedianiX Semiconductor, Inc., Mountain View, California, 1997 to 1999

Senior DSP Firmware Engineer

• Devised three-way dynamic digital crossover (MED25021 product), proficiently designing GUI in Visual Basic and documenting implementation and functional specifications.
• Built configurable bass management for AC-3 and Dolby ProLogic  decoders (Dolby certified).
• Adeptly implemented host controller interface routines for Dolby AC-3 decoder.
• Integrated 3-D audio algorithms such as TruSurround, VMax, and Spatializer and led certification process for TruSurround routine.
• Methodically tested AC-3, ProLogic, and bass management algorithms by analyzing various frequency plots via Audio Precision, and successfully achieved Dolby certification for MED25301.

 

Octel Communications Corporation, Milpitas, California, 1995 to 1997

DSP Software Design Engineer

• Effectively converted TMS320C31 based floating point V.21 (300 bps), V27 (2400 and 4800 bps), and V.29 (7200 and 9600 bps) modem code to fixed point code for TMS320C5X DSP processor.
• Employed impairments such as white noise, SNR and frequency jitter to precisely test fixed point modem code written in C in PC environment.
• Modified existing TMS320C5X voice modules to enable echo canceller configuration capability.

 

University of California at Davis, Signal Processing and Communication Lab, 1993 to 1995

Research & Teaching Assistant

• Analyzed and constructed DSP component of Feher's Quadrature Phase-Shift Key (FQPSK) Transmitter Modulator using Workview and HSpice.
• Fabricated layout of FQPSK modulator and implemented it on ASIC chip using Lager.
• Developed digital Gaussian low pass filter with BTb = 0.5 using ROM look-up table technique, simulated pulse responses in C programming language, and configured on Field Programmable Gate Array (FPGA) Xilinx 4005 chip. 
• Assembled and implemented 25^th order square root raised cosine filter for FQPSK modem on FPGA 4010.
• Contributed technical knowledge and leadership expertise toward teaching and assisting undergraduate engineering students. 

 

 

Pascal, C, Visual Basic, X86 Assembly Language, MatLab, CD2460 Assembly Language, TMS320C5X Assembly Language, TI s C5X AND C3X Debugging Tools, C5X Code Composer, Taskit 100, CodeWright, Audio Precision, Unix, Pspice, Hspice, PowerView, Magic, Lager, Xilinx, Logic Analyzer, Spectrum Analyzer, Spirent DLS 410J loop simulator

 

 

Master of Science in Electrical Engineering, University of California at Davis, 1995

Bachelor of Science in Electrical Engineering, University of California at Davis, 1993